>4. I couldn't find "QorIQ Trust Architecture 2.1 User Guide", >which is pointed out by QorIQ LS1012A reference manual. Is that. > NXP Community

The Qoriq Trust Architecture 2.1 boasts several key features that make it an attractive solution for secure system development:

Run-time integrity checking (RTIC) is a feature that allows the system to verify the integrity of trusted software during execution, not just at boot time. This capability is one of the core features provided by the trust architecture technology.

[ System RAM ] ────── (Background Scan) ──────> [ RTIC Engine ] │ Compares with Baseline Hash │ ▼ [ Match: Continue System ] [ Mismatch: Trigger Alarm ] Cryptographic Key Blobs

Ensuring only signed, authorized code executes. Tamper Resistance: Protecting against physical intrusion.

For general security architecture overview, the NXP community often provides public-facing presentations such as "Introduction to QorIQ Trust Architecture". Conclusion

Ensure only signed, authentic software runs on the platform.

This is typically your primary bootloader (like U-Boot). While stored in external flash, it is signed with a private key. The ISBC verifies this signature before execution. C. Security Engine (SEC)

Securing the boot sequence protects your system at startup, but Trust Architecture 2.1 also enforces security during standard system operations. Run-Time Integrity Checking (RTIC)

QorIQ Trust Architecture 2.1 establishes a hardware root of trust. It ensures that your device only executes authenticated code, protects sensitive data at rest, and detects tampering. The system relies on four core pillars:

Strong partitioning ensures that software entities cannot access or interfere with resources belonging to other software partitions. In the QorIQ Trust Architecture, a "Trusted Partition" exists to distinguish types of trusted software, particularly in QorIQ LS series processors.

The ISBC is the first code executed by the processor upon power-on. It is stored in immutable ROM. Its primary job is to validate the next stage of the bootloader (the ESBC). B. External Secure Boot Code (ESBC)

Also known as the SEC engine, the CAAM offloads intensive cryptographic operations from the main CPU cores. In TA 2.1, the CAAM provides: AES-256, 3DES, and ARC4.

Implementing these features involves several steps detailed in the user guide:

Unlike desktop security that logs errors and continues, TA 2.1’s philosophy is detect and destroy .

The architecture relies on a , anchoring security in immutable components of the Silicon, such as Fuse Arrays (One-Time Programmable - OTP memory). 2. Core Components of Trust Architecture 2.1